In the wireless communication field, a mixer up-converts a baseband signal to a radio frequency signal by mixing the baseband signal with a high frequency (HF) clock, or down-converts a received signal to a baseband signal for subsequent signal processing. However, when a swing of the baseband signal is beyond a predetermined range, a transconducting circuit cannot linearly convert the signal from a voltage form to a current form.
In a differential system, semiconductor manufacturing process variations results in size mismatch between two corresponding transconducting components and thereby incurring a direct current (DC) offset, which then induces local oscillator (LO) leakage. The LO leakage may lead to deterioration in a receive quality of a communication system.
FIG. 1 shows a circuit of a conventional mixer 100. The mixer 100 comprises a differential input circuit including a first input circuit 102, a second input circuit 104, a first transconductance circuit 106, a second transconductance circuit 108, a first converting circuit 110, and a second converting circuit 112. The first input circuit 102 and the second input circuit 104 respectively receive a first input signal Si1 and a second input signal Si2 to generate a first processed signal Sp1 and a second processed signal Sp2. The first transconductance circuit 106 and the second transconductance circuit 108 respectively transconduct the first processed signal Sp1 and the second processed signal Sp2 to a first current signal Sc1 and a second current signal Sc2. The first converting circuit 110 and the second converting circuit 112 respectively receive the first current signal Sc1 and the second current signal Sc2, and generate a first output signal So1 and a second output signal So2 according to a clock signal Slo. In this embodiment, the first input signal Si1 and the second input signal Si2 are a differential pair, and the first output signal So1 and the second output signal So2 are also a differential pair.
In addition, the first input circuit 102 comprises an operational amplifier 1022, an N-type field effect transistor (FET) M1, and an impedance component 1024 which has an end N1 for receiving a reference voltage Vb. The second input circuit 104 comprises an operational amplifier 1042, an N-type FET M2, and an impedance component 1044 which has an end N2 for receiving the reference voltage Vb. The first transconductance circuit 106 and the second transconductance circuit 108 are respectively realized by N-type FETs M3 and M4. The first converting circuit 110 comprises an N-type FET differential pair M5 and M6, and a first load 1102. The N-type FET differential pair M5 and M6 respectively has its gate for receiving the clock signal Slo. The second converting circuit 112 comprises an N-type FET differential pair M7 and M8, and a second load 1122. The N-type FET differential pair M7 and M8 respectively has its gate for receiving the clock signal Slo. Further, the mixer 100 is operated between a power voltage Vdd1 and a ground voltage Vgnd1. Connections between components of the mixer 100 are as shown in FIG. 1, and shall not be described for brevity.
When the first input signal Si1 is inputted at a load end N3 of the operational amplifier 1022, the first processed signal Sp1 corresponding to the first input signal Si1 is outputted to a gate N5 of the N-type FET M3. The N-type FET M3 transconducts the first processed signal Sp1 to the first current signal Sc1 that is then transmitted to the N-type FET differential pair M5 and M6. At this end, a switch between the N-type FET differential pair M5 and M6 is switched according to the clock signal Slo to respectively output information of the first current signal Sc1 to output ends N6 and N7. Likewise, the second input circuit 104 and the N-type FETs M4, M7 and M8 at the same time respectively output information of the second input signal Si2 to the output ends N6 and N7. In FIG. 1, mismatch between the reference voltage generating circuits 102 and 104, and the transconductance circuits 106 and 108, and the converting circuits 110 and 112 is resulted from the fabrication process. As a result a DC offset is incurred that induces an LO leakage in an LO signal generated at an output end of the mixer 100, such that a receive quality of a communication system is undesirably affected.
Since the first input signal Si1 and the second input signal Si2 are respectively connected to load ends N3 and N8 of the operational amplifiers 1022 and 1024, signal swings of the first input signal Si1 and the second input signal Si2 are respectively limited to a bias voltage range of the operational amplifiers 1022 and 1024 that are in normal operation. Therefore, solutions for issues of improving linearity of the mixer 100, reducing influences of DC offset, and increasing an input signal swing in the wireless communication field need to be provided.